The present disclosure relates to a semiconductor memory device, and more particularly to a delay locked loop.
In general, a delay locked loop (DLL) is used in a synchronous dynamic random access memory (DRAM) to improve the operating speed of the synchronous DRAM. The DLL acts to delay an external clock by a predetermined period such that data can be outputted accurately synchronously with the external clock.
This DLL generates an internal clock by compensating the external clock for internal delay factors of the DRAM.
FIG. 1 is a block diagram showing the configuration of a conventional DLL, and FIGS. 2A and 2B are operation timing diagrams of the DLL of FIG. 1.
As shown in FIG. 1, the conventional DLL has two delay lines 130 and 170, one delay line (130) receiving a normal-phase external clock ECLK, and the other delay line (170) receiving a reverse-phase external clock ECLKB. Each of the delay lines 130 and 170 delays the received external clock by a predetermined period. Then, a phase mixer 140 mixes the phases of outputs DLOUT1 and DLOUT2 of the delay lines 130 and 170 and outputs an intermediate-phase internal clock DLLCLK as a result of the mixing.
In detail, an input clock REFCLK is provided as a feedback clock FBCLK1 through the delay line 130, the phase mixer 140 and a replica 150.
At a first loop 110, a phase detector 160 compares the phase of the feedback clock FBCLK1 with that of a reference clock REFCLK.
A controller performs a locking operation by adjusting the delay amount of the delay line 130 until the comparison result of the phase detector 160 indicates that the feedback clock FBCLK1 and the reference clock REFCLK are in phase with each other.
In other words, the controller performs the locking operation by increasing the delay amount of the delay line 130 when the comparison result of the phase detector 160 indicates that the phase of the feedback clock FBCLK1 is ahead of that of the reference clock REFCLK, and decreasing the delay amount of the delay line 130 when the comparison result of the phase detector 160 indicates that the phase of the feedback clock FBCLK1 is behind that of the reference clock REFCLK.
An operation at a second loop 120 is also performed in a similar manner to the operation at the first loop 110. Because a clock CLKB is used as an input to the delay line 170 of the second loop 120, different delay amounts are applied to the delay lines 130 and 170 of the first and second loops 110 and 120, respectively.
FIG. 2A shows an initial timing of the operation of the DLL. Initially, the feedback clock FBCLK1 and a feedback clock FBCLK2 have phases opposite to each other. Each of the two loops of the DLL performs a locking operation of aligning the rising edge of the feedback clock with the rising edge of the reference clock by increasing the delay amount.
Before the first loop is locked, the phase mixer 140 outputs an internal clock DLLCLK of the same phase as that of the output DLOUT1 of the first delay line 130. At this time, as shown in FIG. 2A, the phase of the internal clock DLLCLK is ahead of that of the feedback clock FBCLK1 by a replica delay, and the duty cycle thereof remains not corrected.
FIG. 2B shows a timing of the operation of the DLL after each loop is locked. Because each loop is in a locked state, the rising edges of the feedback clock FBCLK1 and feedback clock FBCLK2 are aligned with the rising edge of the reference clock REFCLK.
When the two loops are locked, the phase mixer 140 outputs an internal clock DLLCLK having an intermediate phase between the phases of the outputs DLOUT1 and DLOUT2 of the two delay lines 130 and 170. Provided that there is a duty cycle error in the reference clock REFCLK, the rising edges of the outputs DLOUT1 and DLOUT2 after the two loops are locked will be in phase with each other, but the falling edges thereof will be out of phase with each other by the duty cycle error. Here, the internal clock DLLCLK with the intermediate phase between the phases of the outputs DLOUT1 and DLOUT2 has a corrected duty cycle. As a result, this internal clock DLLCLK has a high width and a low width which are equal, namely, 50:50.
However, the above-mentioned conventional DLL has a disadvantage in that delay lines are used in two loops, respectively, resulting in an increase in design area.